Source: yosys
Maintainer: Debian Science Maintainers <debian-science-maintainers@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>,
           Sebastian Kuzminsky <seb@highlab.com>,
           Daniel Gröber <dxld@darkboxed.org>
Section: electronics
Priority: optional
Build-Depends: debhelper-compat (= 13),
               dh-python,
               tcl-dev,
               libreadline-dev,
               bison,
               flex,
               gawk,
               libffi-dev,
               pkg-config,
               txt2man,
               iverilog (>= 10.1),
               python3,
               berkeley-abc (>= 1.01+20211229git48498af+dfsg)
Build-Depends-Indep:
               texlive-base,
               texlive-plain-generic,
               texlive-fonts-recommended,
               texlive-fonts-extra,
               texlive-latex-base,
               texlive-latex-extra,
               texlive-font-utils,
               texlive-science,
               texlive-publishers,
               texlive-bibtex-extra,
               lmodern,
               graphviz
Rules-Requires-Root: no
Standards-Version: 4.6.1
Vcs-Browser: https://salsa.debian.org/science-team/yosys
Vcs-Git: https://salsa.debian.org/science-team/yosys.git
Homepage: https://github.com/YosysHQ/yosys

Package: yosys
Architecture: alpha amd64 arm64 armel armhf hurd i386 ia64 kfreebsd-amd64 kfreebsd-i386 m68k mipsel ppc64el riscv64 sh4 x32
# Note: all arches except: powerpc, ppc64, sparc64, hppa, s390x, mips64el
# abc has major problems on bigendian architectures, mips64el is an outlier
# we couldn't get working.
Depends: ${shlibs:Depends},
         ${python3:Depends},
         ${misc:Depends},
         berkeley-abc (>= 1.01+20211229git48498af+dfsg),
         xdot
Description: Framework for Verilog RTL synthesis
 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.

Package: yosys-dev
Architecture: alpha amd64 arm64 armel armhf hurd i386 ia64 kfreebsd-amd64 kfreebsd-i386 m68k mipsel ppc64el riscv64 sh4 x32
Depends: ${shlibs:Depends},
         ${python3:Depends},
         ${misc:Depends},
         tcl-dev,
         libffi-dev,
         libreadline-dev
Description: Framework for Verilog RTL synthesis (development files)
 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the headers and programs needed to build yosys plugins.

Package: yosys-doc
Section: doc
Architecture: all
Depends: ${misc:Depends}
Multi-Arch: foreign
Suggests: yosys
Description: Documentation for Yosys
 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the manual.
